The present invention relates to verifying designs of electronic or digital circuits or the like, and more particularly to a method and system to verify a representation of a circuit design in one computer language, such as a hardware design language (HDL), against another representation of the circuit design in another language, such as C or the like.
When a new device, such as an electronic or digital circuit or the like, is designed, a “golden model” or simulation model may be written in a programming language, such as ANSI-C or a similar programming language. This model together with any embedded software that may run on the device is typically extensively simulated and tested to insure both correct functionality and performance. The device is also typically simulated in a hardware description language (HDL), such as Verilog® or the like. Testing and simulating the circuit in a programming language such as C is easier and faster compared to an HDL language; although, the HDL representation may be used to generate the actual circuit or commercial product. Rather than performing extensive testing on the HDL representation, the product development cycle can be much more efficient using the programming language representation for testing. However, consistency between the programming language model or representation and the HDL model or representation with respect to inputs and outputs must be verified to insure that the models or representations are viable tools and provide accurate results in simulating and testing the new device or circuit. Previous methods of verification can involve complex operations and provide inaccurate results.